An SR latch is shown in figure 13.3. The latch Truth table is shown in the following table. The two inputs, S and R denote ``set'' and ``reset'' respectively. The latch has memory, and the present output is dependent on the state of the latch. Thus the output at instant, denoted by is dependent on output at instant, denoted by .
Students should verify the veracity of the truth table from the figure 13.3.
Note that in state, both and are 0, which seems absurd. Thus, conventionally, the state is said to be ``not allowed''.
A similar latch, known as latch is constructed using NAND gates (as opposed to NOR gates for latch). The students should again check that the working of the latch coheres with that of the truth table.
To avoid ``race'' between the inputs, to have a control on when the input affects the latch, the circuit 13.5 is often implemented.
The inputs have an effect on the latch only when , otherwise, the previous state is maintained. The input may be a clock, so that whatever transitions in and take place before the clock changes to do not affect the outputs, and only when the inputs have become stable is the system affected.