This is an advanced undergraduate/postgraduate course on compiler optimization for multi-core
architectures. The course will cover the following broad topics.
What are multi-core architectures
Issues involved in writing code for the multi-core architectures
How to develop software for these architectures
What are the program optimization techniques
How to build some of these techniques in compilers
OpenMP and parallel programming libraries
Introduction to parallel computers: Instruction Level Parallelism (ILP) vs. Thread
Level Parallelism (TLP); performance issues: brief introduction to cache hierarchy and
Shared memory multiprocessors: general architecture and the problem
of cache coherence; synchronization primitives: atomic primitives; locks: TTS, tickets, array;
barriers: central and tree; performance implications in shared memory programs.
multiprocessors: why CMP (Moore's law, wire delay) ; shared L2 vs. tiled CMP; core
complexity; power/performance; snoopy coherence: invalidate vs. update, MSI, MESI, MOESI,
MOSI;memory consistency models: SC; chip multiprocessor case studies: Intel Montecito and
dual core Pentium 4, IBM power4, Sun Niagara.
Introduction to program optimization: overview of parallelism, shared memory programming;
introduction to OpenMP; data flow analysis, pointer analysis, alias analysis, data dependence
analysis, solving data dependence equations (integer linear programming problem); loop
optimizations; memory hierarchy issues in code optimization.
Operating system issues for multiprocessing: need for pre-emptive OS, scheduling techniques:
usual OS scheduling techniques, threads, distributed scheduler, multiprocessor scheduling , gang
scheduling; communication between processes, message boxes, shared memory; sharing issues
and synchronization, sharing memory and other structures.
Sharing I/O devices, distributed
semaphores, monitors spin locks, implementation techniques for multi-cores; case studies from
applications: digital signal processing, image processing, speech processing.